The world of computer technology has evolved rather rapidly in the past two decades. Interestingly, while the number of languages and programs available has increased, the specific architectures that are used for building microprocessors have not changed that dramatically. What this effectively suggests is that when one looks at the evolution of computers and computer technology, some degree of congruence and similarity can be seen, especially with respect to the specific architecture being utilized.With the realization that computer architecture has not changed that drastically in recent years, there is a clear impetus to examine this issue and explore why this has been so. Utilizing this as a basis for investigation, this research considers the main architectural features of the RISC, or reduced instruction set computer, processor. Specifically, this research considers RISC characteristics, instruction set and formats used, use of register files, instruction level pipelining, RISC processor selection and the advantages and disadvantages of RISC.
[...] Despite the overall utility and viability of RISC, it is clear that this technology is indeed reaching a pinnacle. This is due, in part, to the fact that methods for optimizing the technology have not advanced in recent years. In short the overall speed of the microprocessor has not increased drastically overall. As this technology reaches its apex, it is clear that a new microprocessor architecture will be born. For now it is just a matter of waiting for this new technology to be introduced. [...]
[...] Rather, RISC is indicative of the overall method by which commands are processed by the CPU (“Reduced instruction Finally, in order to make RISC systems efficient and ensure that most commonly used commands large register files are necessary to ensure efficiency. When one considers the overwhelming number of commands that are carried out by the computer and further considers these issues in the context of the ability of the CPU to access these commands, it only stands to reason that large a large number of registers would be necessary to carry out operations in the RISC system. [...]
[...] In older CISC or Complex Instruction Set Computers the microprocessor was responsible for performing all of the actions that are currently encapsulated by computer software. By allocating only specific tasks to the microprocessor and removing the pressure on the system to perform all of the tasks associated with computer software, the RISC system could operate more efficiently and be built cheaper than the CISC microprocessor “RISC keeps instruction size constant, bans the indirect addressing mode and retains only those instructions that can be overlapped and made to execute in one machine cycle or less” In an effort to provide a clear understanding of the RISC architecture, Figure 1 below provides a illustrative representation of how each of these architectures works. [...]
[...] Although the above description provides a clear theoretical understanding of the process of pipelining, it does not accurately describe the processes that occur in RISC pipelining. Defining these processes, one author notes that there are five basic pipeline procedures that are performed by the RISC processor. These include: fetching instructions from memory; reading registers and decoding the instructions; executing the instructions and calculating the address' accessing an operand in data memory; and writing the result to a register (“Pipelining”). The RISC processor is designed so that it will complete one cycle per instruction. [...]
[...] It simplifies translation from the high-level language in which people program into the instruction set that the hardware understands, resulting in a more efficient program (Joy, “Reduced instruction Thus, in this case, the RISC architecture is a clear example of form following function. Because of the simplicity of the design of the microprocessor, the overall performance of the architecture is improved. Instruction Sets and Formats Used In order for the RISC microprocessor to work, specific requirements had to be established for the ISA or instruction set architecture. [...]
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