The gain of SVC depends upon the type of reactive power load for optimum performance. As the load and input wind power conditions are variable, the gain setting of SVC needs to be adjusted or tuned. In this paper, an ANN based approach has been used to tune the gain parameters of the SVC controller over a wide range of load characteristics. The multi-layer feed-forward ANN tool with the error back propagation training method is employed. Loads have been taken as the function of voltage. Analytical techniques have mostly been based on impedance load reduced network models, which suffer from several disadvantages, including inadequate load representation and lack of structural integrity. The ability of ANNs to spontaneously learn from examples, reason over inexact and fuzzy data and provide adequate and quick responses to new information not previously stored in memory has generated high performance dynamical system with unprecedented robustness. ANNs models have been developed for different hybrid power system configurations for tuning the proportional-integral controller for SVC.
Keywords: Performance analysis, profile, trace, reconfigurable computing,FPGA,high level language, C, Carte, Reprogrammability, Recongigurable, hardware, Granularity, Hardware Object
[...] Though these features are compatible with configurable computing applications, they are not sufficient for reconfigurable computing. In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved have some or all of the following features. The more of these features they have, the more flexible can be the system design. ON THE FLY REPROGRAMMABILITY Whenever possible, we'd like to avoid resetting the FPGA, mostly because it takes a lot of time. Ideally, we could just stop the clock going to some or all of the chip, change the logic within that region, and restart the clock. [...]
[...] It was not a commercial success, but was promising enough that Xilinx (the inventor of the Field-Programmable Gate Array, FPGA) bought the technology and hired the Algotronix staf CURRENT SYSTEMS Currently there are a number of vendors with commercially available reconfigurable computers aimed at the high performance computing market; including Cray, SGI and SRC Computers, Inc . The reconfigurable computers are "Estrin" hybrid computers with microprocessors that can be used in traditional CPU cluster computers or coupled to user-programmable FPGAs for hybrid computing. [...]
[...] To compare the effect of various ways to implement an algorithm on the runtime and energy used, some tools allow compiling the same piece of C code for a fixed CPU, a soft processor, or compiling directly to FPGA Reconfigurable computing as a paradigm shift: Hartenstein's anti machine Table Nick Tredennick's Paradigm Classification Scheme Early Historic Computers: Programming Source Resources fixed none Algorithms fixed none von Neumann Computer: Programming Source Resources fixed none Software (instruction Algorithms variable streams) Reconfigurable Computing Systems: Programming Source Resources variable Configware (configuration) Algorithms variable Flow ware (data streams) Computer scientist Reiner Hartenstein describes reconfigurable computing in terms of an anti machine that, according to him, represents a fundamental paradigm shift away from the more conventional von Neumann machine . [...]
[...] This is configurable computing; reconfigurable computing goes one step further. Reconfigurable computing involves manipulation of the logic within the FPGA at run-time. In other words, the design of the hardware may change in response to the demands placed upon the system while it is running. Here, the FPGA acts as an execution engine for a variety of different hardware functions some executing in parallel, others in serial much as a CPU acts as an execution engine for a variety of software threads. [...]
[...] instance, see KressArray Xplorer) to enhance the performance of the device whilst still providing a certain level of flexibility for future adaptation. Examples of this are domain specific arrays aimed at gaining better performance in terms of power, area, throughput than their more generic finer grained FPGA cousins by reducing their flexibility. RATE OF RECONFIGURATION GRANULARITY The granularity of the reconfigurable logic is defined as the size of the smallest functional unit (CLB) that is addressed by the mapping tools. [...]
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